1. Field of the Invention
The present invention pertains to a circuit. More particularly, the present invention pertains to a voltage level shifter.
2. The Prior Arts
For a currently used integrated circuit (IC) system, a core logic unit and an input/output unit therein are generally supplied with different voltages. For example, the core logic unit is typically supplied with a voltage of 1.2 volts while the input/output devices with a voltage of 3.3 volts in a device fabricated by 0.13 μm manufacturing process. Since the voltages supplied to the core logic unit and input/output unit are not identical to each other, a conversion circuit is required to be provided between the two units. Such conversion circuit is generally termed as “voltage level shifter”.
FIG. 1 shows a conventional voltage level shifter. The voltage level shifter 10 includes PMOS transistors PG1 and PG2, NMOS transistors NG1 and NG2 and an inverter INV. Herein, the PMOS transistors PG1 and PG2 are regarded as pull-up transistors while the NMOS transistors NG1 and NG2 are regarded as pull-down transistors. Now, assuming a supply voltage VccH is 3.3 volts and an input voltage Vin at an input I is between 0 and 1.2 volts of rectangular wave. When the input voltage Vin transits from a low level (ex. 0 volt) to a high level (ex. 1.2 volts), the NMOS transistor NG1 is turned on and the PMOS transistor PG2 is also turned on since a gate of the PMOS transistor PG2 is driven to low level. Hence, a high level voltage (i0e. 3.3 volt) is presented at an output node O of the voltage level shifter 10. Therefore, the voltage level shifter 10 is capable of shifting the input voltage Vin (i.e. 1.2 volts) into the output voltage Vout (i.e. 3.3 volts). However, since a specific period is required for a voltage of 0 volt being shifted into 1.2 volts, the PMOS and NMOS transistors PG1,PG2,NG1 and NG2 may not function as desired in the voltage level shifter 10 when their gate voltages are too low (lower than a threshold voltage, about 0.8 volts). In addition, during the time when the PMOS transistor PG2 and NMOS transistor NG2 are approaching to on (or off) and off (or on), contribution of the transistors PG2, NG2 on the output voltage Vout compete. As such, the output voltage Vout is later in speed in reaching the low level, compared with only either of the PMOS transistor PG2 and NMOS transistor NG2 is present, causing distortion of the output wave.
FIG. 2 is provided to explain such case. When the input voltage Vin transits from the low level to the high level, the output voltage Vout is pulled to the high level after a delay time Tr. Also, when the input voltage Vin transits from the high level to the low level, the output voltage Vout decreases to the low level after a delay time Tf.
When noises of different levels are present on the input voltage Vin and thus the real input voltage Vin may not be maintained constant, distortion amount caused from the competition varies, leading to a shift on the transition time of the output voltage Vout, which is called “jiggle”. It is generally desirable to reduce such jiggle so as to have a better fidelity of the output wave with respect to the input wave. In addition, the output wave may vary as the noise amount on the input wave varies since the transistors in the voltage level shifter may function differently at this time as compared to that when no noise is present. It is desired to reduce such output wave deviation.
In addition, since the NMOS transistors NG1, NG2 have a high voltage to endure, which is about 2.5 volts at its maximum, the gates thereof have to be thicker, thus leading to a higher threshold voltage. In this case, the NMOS transistors NG1, NG2 have to have more time to switch from low to high. Therefore, it is desired to have a thinner gate for the pull-down transistors NG1, NG2 so that they may have a faster switching speed.